There is a general need for materials with low dielectric constants (low-k) in the integrated circuit manufacturing industry. Using low-k materials as the intermetal and/or interlayer dielectric of conductive interconnects reduces the delay in signal propagation due to capacitive effects. The lower the dielectric constant of the dielectric, the lower the capacitance of the dielectric and the lower the RC delay in the lines of the IC.
Low-k dielectrics are conventionally defined as those materials that have a dielectric constant lower than that of silicon dioxide, that is k<˜4. Typical methods of obtaining low-k materials include doping silicon dioxide with carbon, various hydrocarbon groups or fluorine.
Low dielectric constant materials (k<3) with improved material properties will enable easier integration into the interconnect stack. For instance, using an organosiloxane (For example: tetramethylcyclotetrasiloxane (TMCTS)) as a precursor in a conventional deposition process, the resulting dielectric will possess a dielectric constant of 2.60-2.95 with a modulus of 5-10 GPa (hardness of 0.8-1.8 GPa) and a typical cracking threshold less than 2.5 μm. It is believed that many applications will require a modulus greater than about 10.0 GPa (hardness of greater than about 2.0 GPa) and cracking thresholds of greater than 4 micrometers. It is not uncommon for a modern IC design to require nine metallization layers, each with a separate dielectric layer. Each of these dielectric layers will have to withstand mechanical-stresses from, for example, chemical-mechanical polishing and/or thermal and mechanical stresses incurred during IC packaging operations. A fragile dielectric may crack or delaminate under these stresses, leading to fewer functional ICs (lower yields) during fabrication. In order to avoid these problems, it is desirable to create a dielectric with a high mechanical strength.